module sys_rgu (
    input sys_clk,
    input arst_n,
    output reg rstn_sync
);

  reg rstn_sync0;

  always @(posedge sys_clk, negedge arst_n) begin
    if (~arst_n) begin
      {rstn_sync0, rstn_sync} <= 2'b0;
    end else begin
      {rstn_sync, rstn_sync0} <= {rstn_sync0, 1'b1};
    end
  end

endmodule
